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fujitsu semiconductor data sheet copyright?2011 fujitsu semiconductor limited all rights reserved 2011.1 memory fram cmos 1 m bit (128 k 8) MB85R1001A descriptions the MB85R1001A is an fram (ferroelectric rando m access memory) chip consisting of 131,072 words 8 bits of nonvolatile memory cells created using ferroelectric process and silicon gate cmos process technologies. the MB85R1001A is able to retain data withou t using a back-up battery, as is needed for sram. the memory cells used in the MB85R1001A can be used for 10 10 read/write operations, which is a significant improvement over the number of read and writ e operations supported by flash memory and e 2 prom. the MB85R1001A uses a pseudo-sram interface that is compatible with conventional asynchronous sram. features ? bit configuration : 131,072 words 8 bits ? read/write endurance : 10 10 times ? operating power supply voltage : 3.0 v to 3.6 v ? operating temperature range : ? 40 c to + 85 c ? data retention : 10 years ( + 55 c) ? package : 48-pin plastic tsop (1) ds501-00003-0v01-e
MB85R1001A 2 ds501-00003-0v01-e pin assignments pin descriptions pin number pin name functional description 1, 2, 4, 5, 8, 18 to 26, 28, 29, 45 a0 to a16 address input pins 33 to 35, 38 to 42 i/o1 to i/o8 data input/output pins 44 ce 1 chip enable 1 input pin 7 ce2 chip enable 2 input pin 6we write enable input pin 48 oe output enable input pin 10, 16, 37 vdd supply voltage pins 13, 27, 46 vss ground pins 3, 9, 11, 12, 14, 15, 17, 30 to 32, 36, 43, 47 nc no connect pins a11 a9 n c a 8 a13 w e ce2 a15 n c v dd n c n c v ss n c n c v dd n c a16 a14 a12 a7 a6 a5 a4 oe n c v ss a10 ce1 n c i/o 8 i/o7 i/o6 i/o5 i/o4 v dd n c i/o3 i/o2 i/o1 n c n c n c a0 a1 v ss a2 a3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 8 19 20 21 22 23 24 4 8 47 46 45 44 43 42 41 40 39 3 8 37 36 35 34 33 32 31 30 29 2 8 27 26 25 (fpt-48p-m48) ( top view )
MB85R1001A ds501-00003-0v01-e 3 block diagram functional truth table note: l = v il , h = v ih , x can be either v il or v ih , hi-z = high impedance : latch address and latch data at falling edge, : latch addres s and latch data at rising edge *1 : oe control of the pseudo-sr am means the valid addres s at the falling edge of oe to read. *2 : we control of the pseudo-sram means the valid address and data at the falling edge of we to write. operation mode ce 1ce2 we oe i/o 1 to i/o 8 supply current standby precharge hxxx hi-z standby (i sb ) xlxx xxhh read l h hl data output operation (i cc ) read (pseudo-sram, oe control* 1 ) lhh write l h lh data input write (pseudo-sram, we control* 2 ) lh h a0 a16 to address latch ro w decoder fram array 131,072 8 col u mn decoder s/a i/o1 to i/o 8 i/o 8 i/o1 to intceb intce2 int w e intoe intce2 intceb ce2 intce2 w e oe ce1
MB85R1001A 4 ds501-00003-0v01-e absolute maximum ratings * : all voltages are referenced to vss (ground 0 v). warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. recommended operating conditions * : all voltages are referenced to vss (ground 0 v). warning: the recommended operating co nditions are required in order to ensure the normal operation of the semiconductor device. all of the device's el ectrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affe ct reliability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application out side the listed conditions are advised to contact their representatives beforehand. parameter symbol rating unit min max power supply voltage* v cc ? 0.5 + 4.0 v input pin voltage* v in ? 0.5 v cc + 0.5 ( 4.0) v output pin voltage* v out ? 0.5 v cc + 0.5 ( 4.0) v operating temperature t a ? 40 + 85 c storage temperature tstg ? 40 + 125 c parameter symbol value unit min typ max power supply voltage* v cc 3.0 3.3 3.6 v high level input voltage* v ih v cc 0.8 v cc + 0.5( 4.0) v low level input voltage* v il ? 0.5 + 0.6 v operating temperature t a ? 40 + 85 c
MB85R1001A ds501-00003-0v01-e 5 electrical characteristics 1. dc characteristics (within recommended operating conditions) *1 : during the measurement of i cc , the address, data in were taken to only change once per active cycle. i out : output current *2 : all pins other than setting pins should be input at the cmos level voltages such as h v cc ? 0.2 v, l 0.2 v. parameter symbol condition value unit min typ max input leakage current | i li | v in = 0 v to v cc tbd a output leakage current | i lo | v out = 0 v to v cc , ce 1 = v ih or oe = v ih tbd a operating power supply current i cc ce 1 = 0.2 v, ce2 = v cc ? 0.2 v, i out = 0 ma* 1 tbd tbd ma standby current i sb ce 1 v cc ? 0.2 v tbd tbd a ce2 0.2 v* 2 oe v cc ? 0.2 v, we v cc ? 0.2 v* 2 high level output voltage v oh i oh = ? 1.0 ma v cc 0.8 v low level output voltage v ol i ol = 2.0 ma 0.4 v
MB85R1001A 6 ds501-00003-0v01-e 2. ac characteristics ? ac test conditions supply voltage : 3.0 v to 3.6 v operating temperature : ? 40 c to + 85 c input voltage amplitude : 0.3 v to 2.7 v input rising time : 5 ns input falling time : 5 ns input evaluation level : 2.0 v / 0.8 v output evaluation level : 2.0 v / 0.8 v output impedance : 50 pf (1) read cycle (within recommended operating conditions) (2) write cycle (within recommended operating conditions) parameter symbol value unit min max read cycle time t rc 150 ns ce 1 active time t ca1 120 ns ce2 active time t ca2 120 ns oe active time t rp 120 ns precharge time t pc 20 ns address setup time t as 0 ns address hold time t ah 50 ns oe setup time t es 0 ns output hold time t oh 0 ns output set time t lz 30 ns ce 1 access time t ce1 100 ns ce2 access time t ce2 100 ns oe access time t oe 100 ns output floating time t ohz 20 ns parameter symbol value unit min max write cycle time t wc 150 ns ce 1 active time t ca1 120 ns ce2 active time t ca2 120 ns precharge time t pc 20 ns address setup time t as 0 ns address hold time t ah 50 ns write pulse width t wp 120 ns data setup time t ds 0 ns data hold time t dh 50 ns write setup time t ws 0 ns
MB85R1001A ds501-00003-0v01-e 7 3. pin capacitance parameter symbol condition value unit min typ max input capacitance c in v in = v out = 0 v, f = 1 mhz, t a = + 25 c 10 pf output capacitance c out 10 pf
MB85R1001A 8 ds501-00003-0v01-e timing diagrams 1. read cycle timing (ce 1, ce2 control) 2. read cycle timing (oe control) t as t ah t es v alid t rp h or l ce1 ce2 t rc t pc a0 to a16 oe i/o1 to i/o 8 t ohz hi-z v alid t oh t lz in v alid in v alid t ca1 t ca2 t ce1, t ce2 a0 to a16 oe i/o1 to i/o 8 t as t ah t rc t oe t ohz hi-z v alid t oh t lz v alid h or l t rp in v alid in v alid t pc ce1 ce2 t ca1 t ca2
MB85R1001A ds501-00003-0v01-e 9 3. write cycle timing (ce 1, ce2 control) 4. write cycle timing (we control) ce1 ce2 t ca2 t ca1 t w c t pc a0 to a16 w e data in t w p t dh hi-z t ah t as t ds v alid h or l v alid h or l t w s a0 to a16 t w p t w c t dh hi-z t ah t as t ds v alid h or l v alid h or l t pc w e data in ce1 ce2 t ca1 t ca2
MB85R1001A 10 ds501-00003-0v01-e power on/off sequence (within recommended operating conditions) notes on use after the ir reflow completed, it is not guaranteed to save the data written prior to the ir reflow. parameter symbol value unit min typ max ce 1 level hold time for power off t pd 85 ns ce 1 level hold time for power on t pu 85 ns power supply rising time t r 0.05 200 ms ce1 > v cc 0. 8 * ce1 : don ' t care ce1 > v cc 0. 8 * tp u tr tpd v cc ce2 3.0 v 1.0 v v ih (min) v il (max) 0 v ce1 ce1 v cc ce2 3.0 v 1.0 v v ih (min) v il (max) 0 v * : ce 1 (max) < v cc + 0.5 v notes: ? use either of ce 1 or ce2, or both for disable control of the device. ? because turning the power-on from an inte rmediate level cause malfunction, when the power is turned on, v cc is required to be started from 0 v. ? if the device does not operate within the specified conditions of read cycle, write cycle, power on/off sequence, memory data can not be guaranteed. ? when turning the power on or off, it is re commended that ce2 is connected to ground to prevent unexpected writing. ce2 0.2 v
MB85R1001A ds501-00003-0v01-e 11 ordering infomation note: please confirm the ordering information with the sales representatives. part number package tbd 48-pin plastic tsop(1) (fpt-48p-m48)
MB85R1001A 12 ds501-00003-0v01-e package dimensions please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ 48-pin plastic tsop lead pitch 0.50 mm package width package length 12.00 mm 12.40 mm lead shape gullwing sealing method plastic mold mounting height 1.20 mm max weight 0.36 g 48-pin plastic tsop (fpt-48p-m48) (fpt-48p-m48) c 2010 fujitsu semiconductor limited f48048sc-1-1 14.00 0.20(.551 .008) #12.00 0.10 0.10 0.05 (.004 .002) (.472 .004) 0.08(.003) 0.50(.020) 0.22 (.009 ) 1 25 24 48 a 0.145 (.006 ) m 0.10(.004) details of a part 0~8 (.024 .006) 0.60 0.15 index (stand off) *12.40 0.10(.488 .004) +0.05 ?0.03 +.002 ?.001 +.002 ?.002 +0.05 ?0.04 1.13 0.07 (.044 .003) (mounting height) 0.25(.010) dimensions in mm (inches). note: the values in parentheses are reference values. note 1) # : resin protrusion. (each side : +0.15 (.006) max). note 2) * : these dimensions do not include resin protrusion. note 3) pins width and pins thickness include plating thickness. note 4) pins width do not include tie bar cutting remainder.
MB85R1001A ds501-00003-0v01-e 13 memo
MB85R1001A 14 ds501-00003-0v01-e memo
MB85R1001A ds501-00003-0v01-e 15 memo
MB85R1001A fujitsu semiconductor limited nomura fudosan shin-yokohama bldg . 10-23, shin-yokohama 2-chome, kohoku-ku yokohama kanagawa 222-0033, japan tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ for further information please contact: north and south america fujitsu semiconductor america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://us.fujitsu.com/micro/ europe fujitsu semiconductor europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ korea fujitsu semiconductor korea ltd. 206 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ asia pacific fujitsu semiconductor asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://www.fujitsu.com/sg/se rvices/micro/semiconductor/ fujitsu semiconductor shanghai co., ltd. rm. 3102, bund center, no.222 yan an road (e), shanghai 200002, china tel : +86-21-6146-3688 fax : +86-21-6335-1605 http://cn.fujitsu.com/fss/ fujitsu semiconductor pacific asia ltd. 10/f., world commerce centre, 11 canton road, tsimshatsui, kowloon, hong kong tel : +852-2377-0226 fax : +852-2376-3269 http://cn.fujitsu.com/fsp/ specifications are subject to change without notice. for further information please contact each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representatives before ordering. the information, such as descriptions of function and applicatio n circuit examples, in this docum ent are presented solely for t he purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu semiconductor does not warrant proper operation of the device with respect to use based on such informa tion. when you develop equipment incorporat ing the device based on such information, you must assume any re sponsibility arising out of such use of the information. fujitsu semiconductor assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic di agrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent ri ght or copyright, or any other right of fujitsu semiconductor or any third party or does fujitsu semiconductor warrant non-infringement of any third-part y's intellectual property right or other ri ght by using such information. fujitsu semiconductor assumes no liab ility for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, persona l use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead directly to death, personal injury , severe physical damage or ot her loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile la unch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersi ble repeater and artificial satellite). please note that fujitsu semiconductor will not be liable against you and/or any thir d party for any claims or damages aris- ing in connection with above-men tioned uses of the products. any semiconductor devices have an inherent ch ance of failure. you must protect against in jury, damage or loss from such failure s by incorporating safety design measures into your facility a nd equipment such as redundancy, fi re protection, and prevention of over- current levels and other abnormal operating conditions. exportation/release of any products described in this document may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited: sales promotion department

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